Sr. Principal Digital Design Verification Lead - R10237881
Description
At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work — and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they're making history.Northrop Grumman Aeronautics systems Sector is seeking a highly skilled Sr. Principal Digital Design Verification Lead to develop and execute verification strategies for complex FPGA-based designs. This role focuses on ensuring functional correctness, performance, and robustness of FPGA implementations through advanced simulation, testbench development, and verification methodologies. This position would be supporting our Core Vehicle Management Systems (CVMS) organization out of our San Diego Ca site. This is a hyrbid position however selected candidate must be from a commutable distance from the San Diego Site.
The ideal candidate has strong experience with SystemVerilog-based verification environments and industry-standard simulation tools such as Questa, along with a deep understanding of digital design and FPGA architectures.
The ideal candidate has strong experience with SystemVerilog-based verification environments and industry-standard simulation tools such as Questa, along with a deep understanding of digital design and FPGA architectures.
Essential Functions:
• Develop and maintain comprehensive verification environments for FPGA designs using SystemVerilog (UVM preferred)
• Create reusable, scalable testbenches for functional and performance verification
• Execute simulation-based verification using tools such as Questa/ModelSim
• Develop directed and constrained-random test cases to achieve high functional coverage
• Analyze simulation results, debug failures, and collaborate with design engineers to resolve issues
• Define and track coverage metrics (functional, code, toggle, etc.)
• Participate in design reviews and provide feedback from a verification perspective
• Support regression automation and continuous integration workflows
• Assist in hardware validation and bring-up when needed
Basic Qualifications:
Bachelor’s degree in Electrical Engineering, Computer Engineering, or another STEM field and 8 years of relevant experience; or Master's degree in Electrical Engineering, Computer Engineering, or another STEM field and 6 years of relevant experience
5 or more years of experience in FPGA verification
Strong proficiency in SystemVerilog and modern verification methodologies (UVM strongly preferred)
Hands-on experience with Questa and/or ModelSim
Solid understanding of digital logic design, RTL (Verilog/VHDL), and FPGA architectures
Experience writing testbenches, assertions (SVA), and coverage models
Familiarity with scripting languages such as Python, Tcl, or Bash for automation
Experience with version control systems (e.g., Git)
Ability to obtain and maintain US Government Secret Clearance
Must have ability to obtain and maintain Program Access (PAR) within a reasonable period of time, as determined by the company to meet its business needs.
Preferred Qualifications:
Digital circuit design experience, including simulation & schematic capture through test and integration
Prior hands-on prototyping and debug experience testing complex digital subsystems, such as complex circuit card development involving FPGAs, and/or embedded processors, and/or high-speed interfaces.
Experience with OVM/UVM Verification methodologies.
Demonstrated ability to translate system performance and operational specifications into hardware requirements, design, and test specifications.
